The circuit device includes an integration period signal generation circuit, a polarity switching signal generation circuit, and first and second integration circuits. The integration period signal generation circuit generates a first integration period signal kept in an active state in the first integration period. The polarity switching signal generation circuit generates a first integration polarity switching signal making a transition at a timing synchronized with the reference clock signal in the first integration period, and a second integration polarity switching signal making a transition a predetermined clock count of the reference clock signal after the transition timing of the first integration polarity switching signal in the first integration period. The first integration circuit performs an integrating process in which an integration polarity is switched at the transition timing of the first integration polarity switching signal in the first integration period. The second integration circuit performs an integrating process in which an integration polarity is switched at the transition timing of the second integration polarity switching signal in the first integration period.