- 专利标题: Fuse array layout pattern and related apparatuses, systems, and methods
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申请号: US16799011申请日: 2020-02-24
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公开(公告)号: US11942167B2公开(公告)日: 2024-03-26
- 发明人: Wei Lu Chu , Jing Wang , Zhiwei Liang , Raghu Sreeramaneni
- 申请人: Micron Technology, Inc.
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 代理机构: TraskBritt
- 主分类号: G11C17/18
- IPC分类号: G11C17/18 ; G11C17/16 ; H10B20/20
摘要:
Systems, methods, and apparatuses relating to interlocking transistor active regions are disclosed. An apparatus includes a gate including electrically conductive material and an active material including a doped semiconductor material. A portion of the active material overlapped by the gate has an at least substantially triangular shape. An apparatus includes a plurality of active materials. Each active material includes tapered ends and a plurality of gates. The plurality of active materials is arranged in an interlocking pattern with at least some tapered ends of the active materials interlocking with at least some others of the tapered ends. The plurality of gates overlaps the interlocked tapered ends of the plurality of active materials.
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