A first pixel circuit and a second pixel circuit are connected to a first data signal line. A third pixel circuit and a fourth pixel circuit are connected to a second data signal line. The first data signal line is connected to a first connection wire provided to a frame region. The second data signal line is connected to a second connection wire provided to the frame region. A sum of resistance values of the first data signal line and the first connection wire is smaller than a sum of resistance values of the second data signal line and the second connection wire.