Invention Grant
- Patent Title: Sparse SIMD cross-lane processing unit
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Application No.: US17972663Application Date: 2022-10-25
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Publication No.: US11966745B2Publication Date: 2024-04-23
- Inventor: Rahul Nagarajan , Suvinay Subramanian , Arpith Chacko Jacob
- Applicant: Google LLC
- Applicant Address: US CA Mountain View
- Assignee: Google LLC
- Current Assignee: Google LLC
- Current Assignee Address: US CA Mountain View
- Agency: Lerner David LLP
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F9/30

Abstract:
Aspects of the disclosure are directed to a cross-lane processing unit (XPU) for performing data-dependent operations across multiple data processing lanes of a processor. Rather than implementing operation-specific circuits for each data-dependent operation, the XPU can be configured to perform different operations in response to input signals configuring individual operations performed by processing cells and crossbars arranged as a stacked network in the XPU. Each processing cell can receive and process data across multiple data processing lanes. Aspects of the disclosure include configuring the XPU to use a vector sort network to perform a duplicate count eliminating the need to configure the XPU separately for sorting and duplicate counting.
Public/Granted literature
- US20230153115A1 Sparse SIMD Cross-lane Processing Unit Public/Granted day:2023-05-18
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