- Patent Title: Stud bump for wirebonding high voltage isolation barrier connection
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Application No.: US17242380Application Date: 2021-04-28
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Publication No.: US11973052B2Publication Date: 2024-04-30
- Inventor: Chien-Chang Li , Hung-Yu Chou , Sheng-Wen Huang , Zi-Xian Zhan , Byron Lovell Williams
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Ronald O. Neerings; Frank D. Cimino
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/48 ; H01L21/56 ; H01L23/31 ; H01L23/495
Abstract:
An electronic device includes a bond wire with a first end bonded by a ball bond to a planar side of a first conductive plate, and a second end bonded by a stitch bond to a conductive stud bump at an angle greater than or equal to 60 degrees. A wirebonding method includes bonding the first end of the conductive bond wire to the first conductive plate includes forming a ball bond to join the first end of the conductive bond wire to a planar side of the first conductive plate by a ball bond, and bonding the second end of the conductive bond wire to the conductive stud bump includes forming a stitch bond to join the second end of the conductive bond wire to the conductive stud bump.
Public/Granted literature
- US20220352111A1 STUD BUMP FOR WIREBONDING HIGH VOLTAGE ISOLATION BARRIER CONNECTION Public/Granted day:2022-11-03
Information query
IPC分类:
