Invention Grant
- Patent Title: Embedded semiconductor region for latch-up susceptibility improvement
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Application No.: US17867453Application Date: 2022-07-18
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Publication No.: US11973080B2Publication Date: 2024-04-30
- Inventor: Chien Yao Huang , Yu-Ti Su
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- The original application number of the division: US15881215 2018.01.26
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/761 ; H01L21/8238 ; H01L29/10 ; H01L29/78 ; H01L21/74

Abstract:
The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.
Public/Granted literature
- US20220352159A1 Embedded Semiconductor Region for Latch-Up Susceptibility Improvement Public/Granted day:2022-11-03
Information query
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