A display panel includes a pixel circuit. An operation process of the pixel circuit includes a first data refresh period, a data adjustment stage, and a second data refresh period set in sequence, the data adjustment stage includes a first data adjustment stage. The first data adjustment stage includes T1 first sub-data adjustment stages set in sequence, each first sub-data adjustment stage includes m1 data writing frames and n1 holding frames. The operation process of the pixel circuit further includes a first data refresh frequency F21 and a second data refresh frequency F22, and F21 T21.