Invention Grant
- Patent Title: Vertical interconnect structures in three-dimensional integrated circuits
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Application No.: US17538029Application Date: 2021-11-30
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Publication No.: US11978723B2Publication Date: 2024-05-07
- Inventor: Tzu-Hsien Yang , Hiroki Noguchi , Hidehiro Fujiwara , Yih Wang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: MERCHANT & GOULD P.C.
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L25/065

Abstract:
A 3D IC structure includes multiple die layers, such as a top die layer and a bottom die layer. The top die layer and/or the bottom die layer each includes devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. The devices on the first and the second die layers are laterally surrounded by, or adjacent, vertical interconnect structures (VIS).
Public/Granted literature
- US20220328455A1 VERTICAL INTERCONNECT STRUCTURES IN THREE-DIMENSIONAL INTEGRATED CIRCUITS Public/Granted day:2022-10-13
Information query
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