A printed wiring board includes a base insulating layer, a conductor layer formed on the base insulating layer and including conductor pads, a solder resist layer formed on the base insulating layer such that the solder resist layer is covering the conductor layer and having openings exposing the conductor pads, respectively, and plating bumps formed on the conductor pads such that each of the plating bumps includes a base plating layer formed in a respective one of the openings of the solder resist layer, and a top plating layer formed on the base plating layer. The plating bumps are formed such that the base plating layer has an upper surface and a side surface including a portion protruding from the solder resist layer and having a rough surface and that the top plating layer has a hemispherical shape and is covering only the upper surface of the base plating layer.