- 专利标题： Memory array architecture having sensing circuitry to drive two matrices for higher array efficiency
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申请号： US17842492申请日： 2022-06-16
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公开(公告)号： US12020745B2公开(公告)日： 2024-06-25
- 发明人: Hongmei Wang , Soichi Sugiura
- 申请人： Micron Technology, Inc.
- 申请人地址： US ID Boise
- 专利权人： Micron Technology, Inc.
- 当前专利权人： Micron Technology, Inc.
- 当前专利权人地址： US ID Boise
- 代理机构： Fletcher Yoder, P.C.
- 主分类号： G11C11/40
- IPC分类号： G11C11/40 ; G11C11/4091 ; G11C11/4097
摘要：
An apparatus may include a first matrix comprising a first plurality of digit lines, a second matrix comprising a second plurality of digit lines, a plurality of sense amplifiers, and a plurality of selector circuits. Each selector circuit of the plurality of selector circuits may be configured to selectively couple a respective sense amplifier to either a first digit line of the first plurality of digit lines or a second digit line of the second plurality of digit lines.
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