A semiconductor module parallel circuit includes: a plurality of power semiconductor modules; and a multilayer substrate that interconnects the plurality of power semiconductor modules, each of the power semiconductor modules includes: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, the multilayer substrate includes: an external connection terminal; first signal terminal connection patterns connected to the first signal terminals of the power semiconductor modules; and second signal terminal connection patterns connected to the second signal terminals of the power semiconductor modules, and inductances of gate wiring for the plurality of power semiconductor modules, from the external connection terminal to the first signal terminal connection pattern and from the second signal terminal connection pattern to the external connection terminal are equal to one another.