Invention Grant
- Patent Title: Method of forming integrated assemblies having transistors configured for high-voltage applications
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Application No.: US17868683Application Date: 2022-07-19
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Publication No.: US12027621B2Publication Date: 2024-07-02
- Inventor: Zia A. Shafi , Luca Laurin , Durga P. Panda , Sara Vigano'
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- The original application number of the division: US16919520 2020.07.02
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L29/66 ; H01L29/78

Abstract:
Some embodiments include an integrated assembly having a first gate operatively adjacent a channel region, a first source/drain region on a first side of the channel region, and a second source/drain region on an opposing second side of the channel region. The first source/drain region is spaced from the channel region by an intervening region. The first and second source/drain regions are gatedly coupled to one another through the channel region. A second gate is adjacent a segment of the intervening region and is spaced from the first gate by an insulative region. A lightly-doped region extends across the intervening region and is under at least a portion of the first source/drain region. Some embodiments include methods of forming integrated assemblies.
Public/Granted literature
Information query
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