Invention Grant
- Patent Title: Multi-gate device and related methods
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Application No.: US17319783Application Date: 2021-05-13
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Publication No.: US12040405B2Publication Date: 2024-07-16
- Inventor: Shih-Hao Lin , Chong-De Lien , Chih-Chuan Yang , Chih-Yu Hsu , Ming-Shuan Li , Hsin-Wen Su
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L21/02 ; H01L21/8238 ; H01L27/092 ; H01L29/06 ; H01L29/161 ; H01L29/24 ; H01L29/423 ; H01L29/66 ; H10B10/00

Abstract:
A method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. In some embodiments, the method further includes forming a gate structure over the fin. Thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. In some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. In various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.
Public/Granted literature
- US20220367725A1 MULTI-GATE DEVICE AND RELATED METHODS Public/Granted day:2022-11-17
Information query
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