- 专利标题： Systems and methods for clock frequency control during low display refresh rates in electronic devices
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申请号： US18296937申请日： 2023-04-06
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公开(公告)号： US12062313B2公开(公告)日： 2024-08-13
- 发明人: Jie Won Ryu , Kingsuk Brahma , Qing Li , Shawn P Hurley , Ce Zhang , Warren S Rieutort-Louis , Feng Wen , Marc J DeVincentis , Zhe Hua , Hyunwoo Nho
- 申请人： Apple Inc.
- 申请人地址： US CA Cupertino
- 专利权人： Apple Inc.
- 当前专利权人： Apple Inc.
- 当前专利权人地址： US CA Cupertino
- 代理机构： Fletcher Yoder, P.C.
- 主分类号： G09G3/20
- IPC分类号： G09G3/20
摘要：
This disclosure is directed towards systems and methods of power saving in electronic displays based on changing clock signal frequencies supplied to the gate-in-panel (GIP) circuitry during extended blanking modes of the electronic display. The display driver circuitry of the display may reduce and/or halt clock signal frequencies sent to GIP circuitry in the display, to reduce power output during extended blanking modes of the electronic display.
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