Invention Grant
- Patent Title: Error detection for programming single level cells
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Application No.: US17871804Application Date: 2022-07-22
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Publication No.: US12067255B2Publication Date: 2024-08-20
- Inventor: Tomer Tzvi Eliash , Yu-Chung Lien
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G01R19/165 ; G06F3/06 ; G06F11/07 ; G11C29/08 ; G11C29/50

Abstract:
Methods, systems, and devices for error detection for programming single level cells of a memory system are described. The memory system may receive a write command for writing data to a block of memory cells and generate a write voltage to write the data to the block of memory cells. The memory system may compare the write voltage to a reference voltage and determine whether the write voltage satisfies a threshold tolerance associated with the reference voltage. The memory system may generate signaling indicating an error associated with writing the data to the block of memory cells, based on determining that the write voltage does not satisfy the threshold tolerance.
Public/Granted literature
- US20240028214A1 ERROR DETECTION FOR PROGRAMMING SINGLE LEVEL CELLS Public/Granted day:2024-01-25
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