- Patent Title: Memory sub-system addressing for data and additional data portions
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Application No.: US17831436Application Date: 2022-06-02
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Publication No.: US12072761B2Publication Date: 2024-08-27
- Inventor: Daniele Balluchi
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F3/06

Abstract:
Systems, apparatuses, and methods related to addressing for data and additional data portions are described herein. In an example method, addressing for data and additional data portions can include accessing data written to a memory device in response to receipt of a first command configured according to a nondeterministic memory interface protocol. The first command can be a compute express link (CXL) protocol compliant command. The example method can further include converting an address associated with the first command to a second command configured according to a standardized deterministic memory interface protocol. The second command can be a DRAM accessible command. The example method can further include accessing a page of memory cells of the memory device in which the data is written, and in which additional data portions associated with the data are written using the converted address associated with the first command.
Public/Granted literature
- US20230393930A1 MEMORY SUB-SYSTEM ADDRESSING FOR DATA AND ADDITIONAL DATA PORTIONS Public/Granted day:2023-12-07
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