Invention Grant
- Patent Title: Logic circuit capable of preventing latch-up
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Application No.: US18143608Application Date: 2023-05-05
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Publication No.: US12087773B2Publication Date: 2024-09-10
- Inventor: Yung-Ju Wen , Han-Chi Liu , Hsin-You Ko
- Applicant: PixArt Imaging Inc.
- Applicant Address: TW Hsin-Chu County
- Assignee: PixArt Imaging Inc.
- Current Assignee: PixArt Imaging Inc.
- Current Assignee Address: TW Hsin-Chu County
- Agency: Bruce Stone LLP
- Agent Joseph A. Bruce
- Main IPC: H01L27/092
- IPC: H01L27/092

Abstract:
There is provided a logic circuit capable of preventing latch-up. The conducting of a parasitic SCR is prevented by doping an additional N+ active region in the N well region of a PMOS transistor and doping an additional P+ active region in the P well region of an NMOS transistor so as to prevent the occurrence of latch-up.
Public/Granted literature
- US20230275089A1 LOGIC CIRCUIT CAPABLE OF PREVENTING LATCH-UP Public/Granted day:2023-08-31
Information query
IPC分类: