Logic circuit capable of preventing latch-up
Abstract:
There is provided a logic circuit capable of preventing latch-up. The conducting of a parasitic SCR is prevented by doping an additional N+ active region in the N well region of a PMOS transistor and doping an additional P+ active region in the P well region of an NMOS transistor so as to prevent the occurrence of latch-up.
Public/Granted literature
Information query
Patent Agency Ranking
0/0