Display panel and display device with reduced charge accumulation in semiconductor layer
Abstract:
A display panel has a display region and a frame region outside the display region. The display region includes a plurality of pixel circuits. The display panel includes a base substrate, a buffer layer, a semiconductor layer, a power signal layer, and an auxiliary circuit layer. The buffer layer is on a side of the base substrate. The buffer layer includes an a-Si layer. The semiconductor layer is on a side of the buffer layer away from the base substrate. The power signal layer is on a side of the semiconductor layer away from the base substrate. The power signal layer includes a plurality of first power voltage lines in the display region, and one first power voltage line of the plurality of first power voltage lines are electrically connected to a corresponding pixel circuit.
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