Invention Grant
- Patent Title: Dual silicide process using ruthenium silicide
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Application No.: US17551381Application Date: 2021-12-15
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Publication No.: US12094785B2Publication Date: 2024-09-17
- Inventor: Thomas Anthony Empante , Avgerinos V. Gelatos , Zhibo Yuan , Liqi Wu , Joung Joo Lee , Byunghoon Yoon
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Servilla Whitney LLC
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L21/285 ; H01L21/768

Abstract:
Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor. The substrate may be pre-cleaned. A ruthenium silicide (RuSi) layer is selectively deposited on the p transistor. A titanium silicide (TiSi) layer is formed on the n transistor and the p transistor. An optional barrier layer may be formed on the titanium silicide (TiSi) layer. The method may be performed in a processing chamber without breaking vacuum.
Public/Granted literature
- US20230187282A1 DUAL SILICIDE PROCESS USING RUTHENIUM SILICIDE Public/Granted day:2023-06-15
Information query
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