Invention Grant
- Patent Title: Detecting a memory write reliability risk without using a write verify operation
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Application No.: US17819826Application Date: 2022-08-15
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Publication No.: US12106812B2Publication Date: 2024-10-01
- Inventor: Yu-Chung Lien , Zhenming Zhou , Tomer Tzvi Eliash
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Harrity & Harrity, LLP
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/10 ; G11C16/24 ; G11C16/32 ; G11C16/34

Abstract:
Implementations described herein relate to detecting a memory write reliability risk without using a write verify operation. In some implementations, a memory device may perform a program operation that includes a single program pulse and that does not include a program verify operation immediately after the single program pulse. The memory device may set a flag value based on comparing a transition time and a transition time threshold. The transition time may be a time to transition from a first voltage to a second voltage during the program operation. The memory device may selectively perform a mitigation operation based on whether the flag value is set to a first value or a second value.
Public/Granted literature
- US20240055060A1 DETECTING A MEMORY WRITE RELIABILITY RISK WITHOUT USING A WRITE VERIFY OPERATION Public/Granted day:2024-02-15
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