- 专利标题: Layouts for conductive layers in integrated circuits
-
申请号: US18156086申请日: 2023-01-18
-
公开(公告)号: US12107048B2公开(公告)日: 2024-10-01
- 发明人: Wan-Yu Lo , Chung-Hsing Wang , Chin-Shen Lin , Kuo-Nan Yang , Meng-Xiang Lee , Hao-Tien Kan , Jhih-Hong Ye
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址: TW Hsinchu
- 专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人地址: TW Hsinchu
- 代理机构: MERCHANT & GOULD P.C.
- 主分类号: H01L23/528
- IPC分类号: H01L23/528 ; H01L23/522
摘要:
Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.
公开/授权文献
- US20230154849A1 LAYOUTS FOR CONDUCTIVE LAYERS IN INTEGRATED CIRCUITS 公开/授权日:2023-05-18
信息查询
IPC分类: