Invention Grant
- Patent Title: Low resistance approaches for fabricating contacts and the resulting structures
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Application No.: US17033471Application Date: 2020-09-25
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Publication No.: US12119387B2Publication Date: 2024-10-15
- Inventor: Gilbert Dewey , Nazila Haratipour , Siddharth Chouksey , Jack T. Kavalieros , Jitendra Kumar Jha , Matthew V. Metz , Mengcheng Lu , Anand S. Murthy , Koustav Ganguly , Ryan Keech , Glenn A. Glass , Arnab Sen Gupta
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/45
- IPC: H01L29/45 ; H01L21/285 ; H01L21/768 ; H01L23/485 ; H01L29/06 ; H01L29/08 ; H01L29/40 ; H01L29/417 ; H01L29/423 ; H01L29/66 ; H01L29/775 ; H01L29/78 ; H01L29/786

Abstract:
Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.
Public/Granted literature
- US20220102521A1 LOW RESISTANCE APPROACHES FOR FABRICATING CONTACTS AND THE RESULTING STRUCTURES Public/Granted day:2022-03-31
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