An electronic device includes at least one processor, a Universal Flash Storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface including a plurality of downstream lanes for transmitting data and a plurality of upstream lanes for transmitting data and storage including a cache memory and a plurality of non-volatile memories. The at least one processor transmits a first control signal to instruct measuring a temperature of the storage and identifying of the measured temperature exceeding a threshold value to the UFS device controller, receives a status signal indicating that the measured temperature exceeds the threshold value from the UFS device controller, and based on the status signal, transmits, to the UFS device controller, a second control signal to instruct that deactivating at least some of the plurality of downstream lanes and upstream lanes, or deactivating the cache memory in the storage.