Invention Grant
- Patent Title: Data-dependent glitch and inter-symbol interference minimization in switched-capacitor circuits
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Application No.: US17952863Application Date: 2022-09-26
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Publication No.: US12132493B2Publication Date: 2024-10-29
- Inventor: Arashk Norouzpourshirazi , Ramin Zanbaghi , Stephen T. Hodapp , Christophe J. Amadi , Ravi K. Kummaraguntla , Dhrubajyoti Dutta
- Applicant: Cirrus Logic International Semiconductor Ltd.
- Applicant Address: GB Edinburgh
- Assignee: Cirrus Logic Inc.
- Current Assignee: Cirrus Logic Inc.
- Current Assignee Address: US TX Austin
- Agency: Jackson Walker L.L.P.
- Main IPC: H03M1/06
- IPC: H03M1/06
Abstract:
A system may include a sampling capacitor and a switch network. The switch network may include one or more first sampling switches electrically coupled to the sampling capacitor and configured to be activated during a first phase of a sampling cycle of the system and one or more second sampling switches electrically coupled to the sampling capacitor and configured to be activated during a second phase of the sampling cycle, wherein the switch network is configured to reset the sampling capacitor to a data-independent and/or signal-independent charge during a reset phase of the sampling cycle.
Public/Granted literature
- US20240106448A1 DATA-DEPENDENT GLITCH AND INTER-SYMBOL INTERFERENCE MINIMIZATION IN SWITCHED-CAPACITOR CIRCUITS Public/Granted day:2024-03-28
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