Invention Grant
- Patent Title: Method for handling exception or interrupt in heterogeneous instruction set architecture and apparatus
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Application No.: US18064543Application Date: 2022-12-12
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Publication No.: US12147813B2Publication Date: 2024-11-19
- Inventor: Yifei Jiang , Siqi Zhao , Bo Wan
- Applicant: HUAWEI TECHNOLOGIES CO., LTD.
- Applicant Address: CN Guangdong
- Assignee: HUAWEI TECHNOLOGIES CO., LTD.
- Current Assignee: HUAWEI TECHNOLOGIES CO., LTD.
- Current Assignee Address: CN Guangdong
- Agency: Fish & Richardson P.C.
- Priority: CN202010539884.3 20200612
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38 ; G06F9/455 ; G06F9/48

Abstract:
A method for handling an exception or interrupt in a heterogeneous instruction set architecture is provided. A physical host to which the method is applied can support two instruction set architectures. When a secondary architecture virtual machine triggers an exception or interrupt, a virtual machine monitor may translate code of the exception or interrupt in a secondary instruction set architecture into code of the exception or interrupt in a primary instruction set architecture. The virtual machine monitor) may identify the code of the exception or interrupt in the primary instruction set architecture. The virtual machine monitor identifies, based on the translated code, a type of the exception or interrupt triggered by the secondary architecture virtual machine, to handle the exception or interrupt.
Public/Granted literature
- US20230124004A1 METHOD FOR HANDLING EXCEPTION OR INTERRUPT IN HETEROGENEOUS INSTRUCTION SET ARCHITECTURE AND APPARATUS Public/Granted day:2023-04-20
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