A semiconductor device including a substrate, first and second active patterns, each including first and second side walls, a field insulation layer surrounding side walls of each of the first and second active patterns, a first dam between the first and second active patterns and having a lower surface lower than an upper surface of the field insulation layer, a second dam spaced apart from the first side wall of the first active pattern and having a lower surface lower than the upper surface of the field insulation layer, a first gate electrode on the first dam between the first and second active patterns, a second gate electrode spaced apart from the first gate electrode, and a first gate cut spaced apart from each of the first side walls of each of the first and second active patterns and intersecting each of the first and second gate electrodes.