- Patent Title: Threshold voltage modulation for gate-all-around FET architecture
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Application No.: US17528863Application Date: 2021-11-17
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Publication No.: US12183798B2Publication Date: 2024-12-31
- Inventor: Steven C. H. Hung , Benjamin Colombeau , Myungsun Kim , Srinivas Gandikota , Yixiong Yang , Jacqueline Samantha Wrench , Yong Yang
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/06 ; H01L29/78 ; H01L29/786
Abstract:
A method of forming a gate stack structure includes forming a dipole metal layer on a high-κ gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-κ gate dielectric layer.
Public/Granted literature
- US20220238680A1 THRESHOLD VOLTAGE MODULATION FOR GATE-ALL-AROUND FET ARCHITECTURE Public/Granted day:2022-07-28
Information query
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