A memory device includes a memory array and control logic to perform operations including identifying a target cell and a set of cells adjacent to the target cell. Each cell of the set of cells is associated with a respective adjacent cell state. The operations further include determining, for each adjacent cell state, a respective interference value, assigning, based on the respective interference value, each adjacent cell state to a respective bin of a set of state information bins, and in response to determining that each bin of the set of state information bins has at least one adjacent cell state assigned to it, and determining a set of read level offsets for reading the target cell. Each read level offset of the set of read level offsets is associated with a respective bin of the set of state information bins.