Invention Grant
- Patent Title: Device architectures with tensile and compressive strained substrates
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Application No.: US17347417Application Date: 2021-06-14
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Publication No.: US12218201B2Publication Date: 2025-02-04
- Inventor: Bich-Yen Nguyen , Christophe Maleville , Walter Schwarzenbach , Gong Xiao , Aaron Thean , Chen Sun , Haiwen Xu
- Applicant: Soitec , National University of Singapore
- Applicant Address: FR Bernin; SG Singapore
- Assignee: Soitec,National University of Singapore
- Current Assignee: Soitec,National University of Singapore
- Current Assignee Address: FR Bernin; SG Singapore
- Agency: TraskBritt
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L21/02 ; H01L21/265 ; H01L21/84 ; H01L27/10 ; H01L27/12 ; H01L29/161 ; H01L29/78
Abstract:
A semiconductor structure, including: a base substrate; an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, and/or silicon germanium, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising: a first plurality of volumes of semiconductor material having a tensile strain of at least about 0.6%; and a second plurality of volumes of semiconductor material having a compressive strain of at least about −0.6%. Also described is a method of preparing a semiconductor structure and a segmented strained silicon-on-insulator device.
Public/Granted literature
- US20220399441A1 DEVICE ARCHITECTURES WITH TENSILE AND COMPRESSIVE STRAINED SUBSTRATES Public/Granted day:2022-12-15
Information query
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