Semiconductor package
Abstract:
A semiconductor package includes a base substrate having a plurality of upper pads and a plurality of first and second lower pads, a semiconductor chip disposed on the base substrate and electrically connected to the plurality of upper pads, a solder resist layer having a plurality of openings exposing a region of each of the plurality of first and second lower pads, the exposed regions of the plurality of first and second lower pads having the same size, a plurality of first external connection conductors respectively disposed on the exposed regions of the plurality of first lower pads and having a first height and a first volume, and a plurality of second external connection conductors respectively disposed on the exposed regions of the plurality of second lower pads and having a second height, greater than the first height, and a second volume, greater than the first volume.
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