The present disclosure provides a gate driving circuit and a display device. An nth stage circuit among a plurality of stage circuits included in a gate driving circuit according to embodiments of the disclosure may include a scan output buffer circuit configured to output a scan signal according to voltages of a Q node and a Qb node, a control circuit including a plurality of transistors to control the voltages of the Q node and the Qb node, the plurality of transistors including a first Q node discharge transistor turned on or off by the voltage of the Qb node to control connection between the Q node and a low-potential voltage node, and a body bias circuit configured to supply a body bias voltage to a body of a first Q node discharge transistor.