Provided is a non-volatile memory device including a first structure including a first substrate; a peripheral circuit; a first insulation structure; a plurality of first bonding pads; and a first interconnect structure; a second structure, which includes a conductive etch stop layer; a common source line layer; a stacked structure including alternately stacked gate layers and interlayer insulation layers; a plurality of channel structures penetrating through a cell region of the stacked structure; a second insulation structure; a plurality of second bonding pads; and a second interconnect structure and bonded to the first structure; and a connection layer including a third insulation structure; an input/output via; and an input/output pad, wherein an interface between the second insulation structure and the third insulation structure is disposed at a vertical level between the top surface and the bottom surface of the conductive etch stop layer.