A D/A converting unit generates a comparative voltage corresponding to a target bit falling within a range from a most significant bit through a least significant bit. A comparator determines a value of the target bit by comparing a differential voltage between an output signal of an input switching unit and a comparative voltage generated by the D/A converting unit with a reference voltage. An integrator integrates a conversion error. In a first conversion operation of converting a first signal, a control unit sets, based on a result obtained by the integrator, the reference voltage for use when the first signal to be provided next time as the output signal by the input switching unit is A/D converted. In a second conversion operation of A/D converting a second signal, the control unit sets the reference voltage at a constant voltage level.