A display panel includes a substrate, a first barrier layer disposed on the substrate, a shielding pattern disposed on the first barrier layer, a second barrier layer covering the shielding pattern and disposed on the first barrier layer, a first active pattern disposed on the second barrier layer and overlapping the shielding pattern in a plan view, a gate electrode disposed on the first active pattern, an emission control line disposed on the first active pattern and adjacent to one side of the gate electrode in a plan view, and an upper compensation control line disposed on the emission control line and adjacent to the other side of the gate electrode in a plan view.