An LSI device comprises: an FIFO buffer in which transmitting data is written, and from which the transmitting data is output in the order of the writing; a controller for transmitting the transmitting data to the FIFO buffer in response to a write interrupt signal; and an FIFO controller for generating and outputting the write interrupt signal to the controller in accordance with a state wherein the FIFO buffer is empty, and for variably setting a variable interval for the write interrupt signal. According to the present invention, since the FIFO controller can generate the write interrupt signal in accordance with the state wherein the FIFO buffer is empty, and can set a variable interval for the write interrupt signal, an optimal writing process for the system can be implemented, and the frequency at which communication errors occur can be reduced.