A circuit architecture and a method for performing a trimming operation directly on an application board, or after the operation of packaging integrated electronic devices. The circuit architecture includes at least one non-volatile memory unit (3) having non-volatile memory elements (5) and a circuit (17,19) for modifying the state of the memory elements (5), a first multifunctional input pin (8) whereon a sequence (25) of trimming data is received, a second multifunctional input pin (9) whereon a timing signal of the trimming operations is received, and an additional access pin (7) for switching the circuit architecture operation from a normal mode over to a trimming mode. This circuit architecture further includes a volatile memory unit (2) associated with the non-volatile memory unit (3) for storing the non-volatile memory (3) state at power-on or at a simulating phase, and storing the sequence (25) of trimming data at a programming phase; an interface (6) is provided between the first multifunctional input pin (8), the second multifunctional input pin (9), and the additional access pin (7), the at least one non-volatile memory unit (3), and the volatile memory unit (2), for initially storing the sequence of trimming data (25) into the volatile memory unit (2) and subsequently timing the trimming operation.