Invention Application
US20020175697A1 Efficient parallel testing of semiconductor devices using a known good device to generate expected responses
失效
使用已知的良好器件对半导体器件进行有效的并行测试以产生预期响应
- Patent Title: Efficient parallel testing of semiconductor devices using a known good device to generate expected responses
- Patent Title (中): 使用已知的良好器件对半导体器件进行有效的并行测试以产生预期响应
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Application No.: US10208173Application Date: 2002-07-29
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Publication No.: US20020175697A1Publication Date: 2002-11-28
- Inventor: Charles A. Miller , Richard S. Roy
- Applicant: FormFactor, Inc.
- Applicant Address: null
- Assignee: FormFactor, Inc.
- Current Assignee: FormFactor, Inc.
- Current Assignee Address: null
- Main IPC: G01R031/26
- IPC: G01R031/26

Abstract:
A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the channel while the tester is writing data as part of a test sequence to locations in the known good device. In response, the interface circuitry writes the data to corresponding locations in each of a number of devices under test (DUTs). The interface circuitry monitors the channel while the tester is reading from the locations in the known good device (KGD), and in response performs a comparison between DUT data read from the corresponding locations in the DUTs and expected responses obtained form the KGD.
Public/Granted literature
Information query