Invention Application
US20020185696A1 Lateral DMOS structure with lateral extension structure for reduced charge trapping in gate oxide 失效
具有横向延伸结构的横向DMOS结构,用于减少栅极氧化物中的电荷捕获

  • Patent Title: Lateral DMOS structure with lateral extension structure for reduced charge trapping in gate oxide
  • Patent Title (中): 具有横向延伸结构的横向DMOS结构,用于减少栅极氧化物中的电荷捕获
  • Application No.: US10104342
    Application Date: 2002-03-22
  • Publication No.: US20020185696A1
    Publication Date: 2002-12-12
  • Inventor: James D. Beasom
  • Applicant: INTERSIL AMERICAS INC.
  • Applicant Address: null
  • Assignee: INTERSIL AMERICAS INC.
  • Current Assignee: INTERSIL AMERICAS INC.
  • Current Assignee Address: null
  • Main IPC: H01L029/76
  • IPC: H01L029/76
Lateral DMOS structure with lateral extension structure for reduced charge trapping in gate oxide
Abstract:
A high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage. The semiconductor device comprising a semiconductor body, an extended drain region formed in the semiconductor body, source and drain pockets, a top gate forming a pn junction with the extended drain region, an insulating layer on a surface of the semiconductor body and a gate formed on the insulating layer. In addition, a higher-doped pocket of semiconductor material is formed within the top gate region that has a higher integrated doping than the rest of the top gate region. This higher-doped pocket of semiconductor material does not totally deplete during device operation. Moreover, the gate controls, by field-effect, a flow of current through a channel formed laterally between the source pocket and a nearest point of the extended drain region.
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