Invention Application
US20030233605A1 Method and circuit for interlacing numeric data to reduce transmission errors 有权
用于隔行数字数据以减少传输错误的方法和电路

  • Patent Title: Method and circuit for interlacing numeric data to reduce transmission errors
  • Patent Title (中): 用于隔行数字数据以减少传输错误的方法和电路
  • Application No.: US10424166
    Application Date: 2003-04-25
  • Publication No.: US20030233605A1
    Publication Date: 2003-12-18
  • Inventor: Charaf Hanna
  • Applicant: STMicroelectronics SA
  • Applicant Address: FR Montrouge
  • Assignee: STMicroelectronics SA
  • Current Assignee: STMicroelectronics SA
  • Current Assignee Address: FR Montrouge
  • Priority: FR0205290 20020426
  • Main IPC: G11C029/00
  • IPC: G11C029/00
Method and circuit for interlacing numeric data to reduce transmission errors
Abstract:
A method for interlacing digital data to reduce transmission errors includes dividing a stream of digital data into consecutive blocks of bits, and interlacing each block of bits by writing to an interlacing table. The interlacing table is arranged in the form of rows and columns of memory addresses, with a number of the rows and columns corresponding to predetermined interlacing parameters. The access sequences to the memory addresses for interlacing the blocks of bits are different from each other. The method further includes reading a block of bits in the interlacing table according to a memory addresses access sequence, and also writing bits to a consecutive block of bits according to the memory addresses access sequence during the reading.
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