Invention Application
- Patent Title: Method and relative circuit for incrementing, decrementing or two's complementing a bit string
- Patent Title (中): 用于递增,递减或二进制补码的方法和相关电路
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Application No.: US10651075Application Date: 2003-08-28
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Publication No.: US20040073586A1Publication Date: 2004-04-15
- Inventor: Daniele Lo Iacono
- Applicant: STMicroelectronics S.r.I.
- Applicant Address: IT Agrate Brianza (MI)
- Assignee: STMicroelectronics S.r.I.
- Current Assignee: STMicroelectronics S.r.I.
- Current Assignee Address: IT Agrate Brianza (MI)
- Priority: EP02425538.2 20020830
- Main IPC: G06F007/38
- IPC: G06F007/38

Abstract:
A method for incrementing, decrementing or two's complementing a first string of bits includes generating an auxiliary string of bits as a function of the first string, and logically combining the auxiliary string with the first string to generate a corresponding output string. A least significant bit of the auxiliary string is independent from the bits of the first string, and any other bit of the auxiliary string. The method is particularly convenient for generating an overflow flag when the number to be output exceeds the representation interval. An overflow flag is generated by logically combining the most significant bits of the first and auxiliary strings.
Public/Granted literature
- US07395305B2 Method and relative circuit for incrementing, decrementing or two's complementing a bit string Public/Granted day:2008-07-01
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