Invention Application
- Patent Title: Method for testing chips on flat solder bumps
- Patent Title (中): 在平坦焊料凸块上测试芯片的方法
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Application No.: US10688418Application Date: 2003-10-17
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Publication No.: US20040087046A1Publication Date: 2004-05-06
- Inventor: Madhav Datta , Peter A. Gruber , Judith M. Rubino , Carlos J. Sambucetti , George F. Walker
- Applicant: International Business Machines Corporation.
- Applicant Address: null
- Assignee: International Business Machines Corporation.
- Current Assignee: International Business Machines Corporation.
- Current Assignee Address: null
- Main IPC: H01L021/66
- IPC: H01L021/66

Abstract:
A method for testing integrated circuit chips with probe wires on flat solder bumps and IC chips that are equipped with flat solder bumps are disclosed. In the method, an IC chip that has a multiplicity of bond pads and a multiplicity of flat solder bumps are first provided in which each of the solder bumps has a height less than null of its diameter on the multiplicity of bond pads. The probe wires can thus be easily used to contact the increased target area on the solder bumps for establishing electrical connection with a test circuit. The probe can further be conducted easily with all the Z height of the bumps are substantially equal. The height of the solder bumps may be suitably controlled by either a planarization process in which soft solder bumps are compressed by a planar surface, or solder bumps are formed in an in-situ mold by either a MSS or an electroplating process for forming solder bumps in the shape of short cylinders. When the MSS method is used for planting the bumps, solder bumps are transferred onto the wafer surface in a substantially flattened hemi-spherical shape.
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