发明申请
US20050020052A1 Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
有权
用于制造用于芯片级封装的热适应性半导体芯片布线结构的方法
- 专利标题： Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
- 专利标题（中）： 用于制造用于芯片级封装的热适应性半导体芯片布线结构的方法
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申请号： US10925302申请日： 2004-08-24
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公开(公告)号： US20050020052A1公开(公告)日： 2005-01-27
- 发明人: Jin-Yuan Lee , Eric Lin
- 申请人： Jin-Yuan Lee , Eric Lin
- 专利权人： Megic Corporation
- 当前专利权人： Megic Corporation
- 主分类号： H01L21/60
- IPC分类号： H01L21/60 ; H01L23/31 ; H01L23/485 ; H01L21/44
摘要：
A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical spacers and the substrate. The conductive layer is patterned to form conductive bonding locations overlying the temporary vertical spacers. The temporary vertical spacers are etched away to create voids underlying the conductive bonding locations.
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