Invention Application
US20050027963A1 System and method for employing a process identifier to minimize aliasing in a linear-addressed cache
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用于使用进程标识符来最小化线性寻址高速缓存中的混叠的系统和方法
- Patent Title: System and method for employing a process identifier to minimize aliasing in a linear-addressed cache
- Patent Title (中): 用于使用进程标识符来最小化线性寻址高速缓存中的混叠的系统和方法
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Application No.: US10917449Application Date: 2004-08-13
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Publication No.: US20050027963A1Publication Date: 2005-02-03
- Inventor: Herbert Hum , Stephan Jourdan , Per Hammarlund
- Applicant: Herbert Hum , Stephan Jourdan , Per Hammarlund
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F12/08

Abstract:
A system and method for reducing linear address aliasing is described. In one embodiment, a portion of a linear address is combined with a process identifier, e.g., a page directory base pointer to form an adjusted-linear address. The page directory base pointer is unique to a process and combining it with a portion of the linear address produces an adjusted-linear address that provides a high probability of no aliasing. A portion of the adjusted-linear address is used to search an adjusted-linear-addressed cache memory for a data block specified by the linear address. If the data block does not reside in the adjusted-linear-addressed cache memory, then a replacement policy selects one of the cache lines in the adjusted-linear-addressed cache memory and replaces the data block of the selected cache line with a data block located at a physical address produced from translating the linear address. The tag for the cache line selected is a portion of the adjusted linear address and the physical address produced from translating the linear address.
Public/Granted literature
- US06990551B2 System and method for employing a process identifier to minimize aliasing in a linear-addressed cache Public/Granted day:2006-01-24
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