发明申请
- 专利标题： Method of manufacturing semiconductor integrated circuit device having capacitor element
- 专利标题（中）： 具有电容元件的半导体集成电路器件的制造方法
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申请号： US10951940申请日： 2004-09-29
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公开(公告)号： US20050042827A1公开(公告)日： 2005-02-24
- 发明人: Naotaka Hashimoto , Yutaka Hoshino , Shuji Ikeda
- 申请人： Naotaka Hashimoto , Yutaka Hoshino , Shuji Ikeda
- 优先权： JP7-181513 19950718
- 主分类号： G11C11/412
- IPC分类号： G11C11/412 ; H01L21/8244 ; H01L23/522 ; H01L27/10 ; H01L27/11 ; H01L21/336
摘要：
In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.
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