发明申请
- 专利标题: Wafer-level moat structures
- 专利标题(中): 晶圆级护城河结构
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申请号: US10672165申请日: 2003-09-26
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公开(公告)号: US20050070083A1公开(公告)日: 2005-03-31
- 发明人: Michael Johnson , Peter Elenius , Deok Kim
- 申请人: Michael Johnson , Peter Elenius , Deok Kim
- 专利权人: FLIP CHIP TECHNOLOGIES, L.L.C.
- 当前专利权人: FLIP CHIP TECHNOLOGIES, L.L.C.
- 主分类号: H01L
- IPC分类号: H01L20060101 ; H01L21/44 ; H01L21/60 ; H01L21/66 ; H01L23/31 ; H01L23/485
摘要:
A wafer-level CSP (200) includes at least one die (202) from a wafer. The wafer-level CSP has a plurality of solder ball pads (206), a solder ball (308) at each solder ball pad and a polymer collar (310) around each solder ball. A moat (204) is formed in the surface of a polymer layer (412) disposed on the wafer during manufacturing of the wafer-level CSP. A temporarily liquified residual (502) from the polymer collar, which occurs while the wafer is heated to the reflow temperature of the solder ball, flows from the polymer collar. The moat acts as a barrier to material flow, limiting the distance that the residual spreads while liquified. The residual from the polymer collar remains within a region (314) defined by the moat. A full-depth moat (312) extends completely through the polymer layer. Alternatively, a partial-depth moat (712 and 912) extends partially through the polymer layer. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. §1.72(b).
公开/授权文献
- US07126164B2 Wafer-level moat structures 公开/授权日:2006-10-24
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