发明申请
US20050076194A1 Unified instruction pipeline for power reduction in a digital signal processor integrated circuit
有权
用于数字信号处理器集成电路中的功率降低的统一指令流水线
- 专利标题: Unified instruction pipeline for power reduction in a digital signal processor integrated circuit
- 专利标题(中): 用于数字信号处理器集成电路中的功率降低的统一指令流水线
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申请号: US10651234申请日: 2003-08-28
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公开(公告)号: US20050076194A1公开(公告)日: 2005-04-07
- 发明人: Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle Philhower , Manoj Mehta , Kenneth Malich
- 申请人: Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle Philhower , Manoj Mehta , Kenneth Malich
- 主分类号: G06F1/26
- IPC分类号: G06F1/26 ; G06F7/38 ; G06F12/00 ; G06F13/38
摘要:
Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.