Invention Application
US20050079638A1 System and method for reducing shorting in memory cells 有权
用于减少存储器单元短路的系统和方法

  • Patent Title: System and method for reducing shorting in memory cells
  • Patent Title (中): 用于减少存储器单元短路的系统和方法
  • Application No.: US10684967
    Application Date: 2003-10-14
  • Publication No.: US20050079638A1
    Publication Date: 2005-04-14
  • Inventor: Joel DrewesJames Deak
  • Applicant: Joel DrewesJames Deak
  • Main IPC: H01L21/00
  • IPC: H01L21/00 H01L27/22
System and method for reducing shorting in memory cells
Abstract:
An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce the likelihood of electrical shorting across the barrier layers of the memory cells, spacers can be formed around the upper conductive layer and, after the layers of the magnetic memory cells have been etched, the memory cells can be oxidized to transform any conductive particles that are deposited along the sidewalls of the memory cells as byproducts of the etching process into nonconductive particles. Alternatively, the lower conductive layer can be repeatedly subjected to partial oxidation and partial etching steps such that only nonconductive particles can be thrown up along the sidewalls of the memory cells as byproducts of the etching process.
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