Invention Application
- Patent Title: Method for discrete gate sizing in a netlist
- Patent Title (中): 网表中离散门尺寸的方法
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Application No.: US10683628Application Date: 2003-10-10
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Publication No.: US20050081175A1Publication Date: 2005-04-14
- Inventor: William Scott , Viktor Lapinskii
- Applicant: William Scott , Viktor Lapinskii
- Main IPC: G06F9/45
- IPC: G06F9/45 ; G06F17/50

Abstract:
A set of gate sizes for a netlist having a plurality of gates wherein for each of the gates a number of discrete gate sizes is available is selected such that the selection minimizes worst slack in the netlist. A current gate size for each gate is selected and an a current weight assigned to each one of the timing edges in the netlist. A new gate size is selected for each one of the gates from one of the current gate size and second one of the available gates sizes wherein such selection of each new gate size minimizes a sum of weighted delays obtained over all timing edges. The minimum sum of weighted delays is obtained from a min-cut in a timing flow graph. The results of the min-cut are used in the next iteration and re-iterating occurs until an exit criteria is determined.
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