CPU 16 and a memory controller 15 increment a writing address from a starting address every time when data is written into a shock memory 14, and increment a reproducing address from a starting address, thereby writing data read out by a pickup 12 to the writing address in the shock memory 14. Further, CPU 16 and the memory controller 15 suspend operation for reading out data from the shock memory 14 until the writing address reaches an accumulation judging address, and start the operation for reading out data from the reproducing address of the shock memory 14 when the writing address has reached the accumulation judging address. Even if a pickup for reading data from a recording medium such as CD is in a transient state from a stop state or from a fast forward state to a reproducing state, generation of a disconnected sound is prevented.