Invention Application
- Patent Title: Capacitance multiplier
- Patent Title (中): 电容倍增器
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Application No.: US10941357Application Date: 2004-09-15
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Publication No.: US20050099221A1Publication Date: 2005-05-12
- Inventor: Young-Jin Kim , In-Chul Hwang , Han-Il Lee , Jae-Heon Lee
- Applicant: Young-Jin Kim , In-Chul Hwang , Han-Il Lee , Jae-Heon Lee
- Priority: KR2003-0063579 20030915; KR2004-0000228 20040105
- Main IPC: H03H11/48
- IPC: H03H11/48 ; G06G7/16

Abstract:
A capacitance multiplier includes a self-biasing active load for generating a stable bias voltage without a separate current bias. In addition, the capacitance multiplier includes a cascode load within a multiplying section for increasing the output resistance and in turn the charging/discharging efficiency. Furthermore, the capacitance multiplier is implemented with a plurality of multiplying paths to reduce effects of noise for more stable generation of the multiplied capacitance.
Public/Granted literature
- US07113022B2 Capacitance multiplier Public/Granted day:2006-09-26
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